Various different types of system architectures can be used to build a packet/cell switching fabric. One type of system architecture is the shared bus architecture shown in FIG. 1A. Shared bus architectures include circuit boards 11 having multiple I/O buffers 12 that are coupled to a shared bus 10. Another type of system architecture is the shared memory architecture shown in FIG. 1B. Shared memory architectures include switch ports 21, a central switch fabric 22 and a shared memory 23. Yet another type of system architecture is the output buffered architecture shown in FIG. 1C. Output buffered architectures include switch ports 31 that have an output buffer 32 and a central switch fabric 33.
Shared bus architectures cannot practically be scaled to handle high bandwidth applications since data is transmitted in a broadcast fashion, requiring that each circuit board 11 wait its turn before transmitting on the shared bus 10. Shared memory and output buffered architectures are not easily scaled for two reasons: (1) the memory access speed of shared memory 23 (or output buffers 32), must be as fast as the overall bandwidth of central switch fabric 22 (or central switch fabric 33), and (2) shared memory 23 and output buffers 32 must be very large for packet/cell switching applications.
One type of system architecture that is more scalable and flexible than the architectures shown in FIGS. 1A-1C is the cross-point fabric with buffered input/output architecture shown in FIG. 1D. The cross-point fabric with buffered input/output architecture includes a plurality of line cards 41, each having an input/output (I/O) buffer 42, and a switch card 45, which includes a cross-point switch fabric 43 and an arbiter 44. Without an efficient and fast arbiter, the cross-point architecture with input/output buffer can become blocking. With very high-speed packet/cell transmission rates, it can be challenging to design an efficient arbitration algorithm that achieves 100% throughput for real life data network traffic.
The above-described packet switching technologies are further complicated if variable length packets are allowed. Most high-speed packet/cell switching technologies, such as those used in connection with the architectures of FIGS. 1A-1D require that variable length packets must first be padded into a fixed length internal packet/cells before switching. This padding process can add as much as 30% of transmission overhead to the switched cell/packet. Moreover, the complex arbiter 44 of the traditional cross-point fabric with buffered input/output architecture must be made even more complex to support variable length packets.
It would therefore be desirable to have an improved packet switching technology that overcomes the above-described deficiencies of conventional packet switching technologies. It would further be desirable to have a system that is bandwidth scalable. It would also be desirable to have a system that reduces the transmission overhead of variable length packets.